THINING PROCESS - EQUIPMENT & MATERIALS

Memory, CIS, and power electronics are driving the wafer thinning equipment market, before a new wave of innovation by 2025

Extracted from Thinning Equipment Technology & Market Trends for Semiconductor Devices report, Yole Développement

OUTLINES:

  • Demand for thinned wafers is growing considerably: to follow the miniaturization trends while improving the performances of the devices, semiconductor substrates are thinned down with final thicknesses in the tens of µm.
  • Yole Développement announces a more than 5% CAGR (1)  between 2019 and 2025 to reach more than 135 million thinned wafers at the end of the period.
  • The market is mainly pushed by memory, CIS and power SiC components as well as LED and laser diodes.
  • The thinning equipment market is dominated by the two major grinding & CMP equipment suppliers, DISCO, ACCRETECH. They are followed by Revasum and Ebara.
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“The demand for thinned wafers continues to increase owing to miniaturization associated with greater performance driven by a wide range of applications, such as stacked packages within mobile devices and other consumer products,” explains Amandine Pizzagalli, Technology & Market Analyst at Yole Développement (Yole).According to the new Thinning Equipment Technology & Market Trends for Semiconductor Devices report released by Yole today, the thinned wafer market is showing a significant growth from 100 million to more than 135 million thinned wafers.
In parallel, the market research and strategy consulting company announces almost10% CAGR during the same period for the overall thinning equipment market. Analysts deeply focused on the technical issues and market trends. According Yole’s semiconductor manufacturing team, this industry was worth almost US$461 million in 2019 and will exceed almost US$792 million by 2025 mainly generated by memory, CIS and power SiC components as well as LED and laser diodes.
The Thinning Equipment Technology & Market Trends for Semiconductor Devices report is a comprehensive analysis of the major applications currently using thinning methods. It details attractive applications as well as the key benefits and added value of thinning technology in the semiconductor field. Yole’s analysts deliver today a relevant study of this industry with accurate market forecasts (breakdown by device type, by substrate type and by equipment technology. The competitive landscape including the identification of the key players, their market positioning and strategy is also well described in this new semiconductor manufacturing report.
“With this new report, our aim was to cover the different equipment used for thinning down and polish the semiconductor wafer substrates,”explains Gaël Giusti, PhD., Technology & Market Analyst at Yole. “The scope was focused on the back-end part for semiconductor devices industry. We also added thin film layers market segment. Moreover, this report was an opportunity to point out the market drivers as well as the limitations of each technology”.
What is the status of the thinning technologies today? Behind the existing and emerging technologies, who are the main companies involved? With a strong growth between 2019 and 2025 in volume and a new wave of innovations after 2025, how will each market segment evolve? Yole’s semiconductor manufacturing analysts are pleased to deliver today a snapshot of the thinning technologies and related applications.

Today, most semiconductor wafers are thinned down to a range of 100 µm-200 µm especially when it comes to memory, CIS and power applications.
However, some silicon wafers are thinned down well below 100 µm in HVM , including some 3D stacked memory devices, CIS and power devices. The total memory architecture thickness varies typically from 50 µm to 400 µm depending on the manufacturer and the packaging technology. For instance, standard memory, like DRAM or 2D NAND, uses silicon wafers that are thicker than 200 µm, while 3D stacked DRAM keeps moving downward, from 50 µm to 30 µm thick silicon substrates by 2025. Incidentally, the 30 µm to 50 µm thickness range is the one in which the largest number of thinned wafers is expected by 2025.
Meanwhile, BSI CIS wafers are thinned down below 10 µm thickness and are today the thinnest wafers across all semiconductor applications.
“The thickness of power devices depends on applied voltage as well as semiconductor substrate type,”explains Amandine Pizzagalli from Yole. And she adds: “From a wafer substrate point of view, Si-based MOSFETs involve wafer thickness of around 50 µm to 55 µm on 300 mm diameter wafers in HVM with a trend towards thinning down to 30 µm. Wafer thicknesses for SiC-based devices are rarely lower than 200 µm even though thickness reduction is expected to go down to 100 µm/110 µm in the next few years.”
In parallel, typical wafer thickness for MEMS sensors is today in a range of 200 µm to 350 µm, especially for inertial MEMS.
At the end, RF wafers devices are in the range of 140 µm and 200 µm and are opposite to every other the semiconductor devices in terms of thickness reduction. RF device wafers are getting thicker, with the thickness depending on whether wire bonding or flip-chip packaging will be more widely adopted by the industry.

“Myriad thinning technology steps are applied for the fabrication of semiconductor devices,” comments Gaël Giusti from Yole. At the back-end wafer stage, thinning methods are employed for thinning down the wafers and sometimes even removing the substrate, for LEDs on silicon for example. Although there are similar and common drivers for thinning’s applicability in semiconductor applications, the reasons for using such techniques differ from one device to another and depend on the end-applications. “This is a critical point as it demonstrates that a change in architecture or a disruptive technology with potential large volumes involved can have a tremendous impact on the wafer thinning equipment market,”explains Gaël Giusti.
The microLED market, should it take off and should it use back thinning technologies, could give a significant boost both to wafer-starts and to the corresponding equipment market. The same can be said for CIS, 3D sensing applications or a widespread shift to SiP technology.
As of today and in the case of MEMS devices, such components are typically composed of a stack of a sensor element wafer, a cap and an ASIC. All three wafers must be thinned to reduce the size of the device.
With respect to power devices, thin wafers are needed here since reduced thickness lowers on resistance, improves current carrying capability and minimizes power consumption.
On the other hand, CMOS image sensor wafers are thinned down for TSV packaging where thinning is needed to achieve a very small form factor. BSI with extreme thinning below 10 µm enhances light sensitivity, while hybrid stack and triple stack architectures are pushing the boundaries further.
Traditional LED fabrication also requires a thinning or a removal step at the back-end for miniaturization and easier dicing/singulation. Laser diode requirements are much less stringent but the emergence of high-power VCSELs demands much thinner wafers for enhanced heat management. In the case of memory devices, further thickness reduction is driven by the need to maximize memory capacity of single packages, improved data transfer rates as well as power consumption mostly fueled by mobile applications.

All year long, Yole Développement publishes numerous semiconductor equipment and materials reports. Yole’s experts also propose key presentations through a powerful program of events. Discover them on i-Micronews. Stay tuned!

Note:
(1) In volume

Acronyms

CAGR : Compound Annual Growth Rate
CIS : CMOS Image Sensors
SiC : Silicon Carbide
HVM : High Volume Manufacturing
DRAM : Dynamic Random Access Memory
BSI : Back-Side Illumination
MEMS : Micro Electro Mechanical System
SiP : System in Package
ASIC : Application Specific Integrated Circuit


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